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M59MR032C M59MR032D
32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst) 1.8V Supply Flash Memory
s
SUPPLY VOLTAGE - VDD = VDDQ = 1.65V to 2.0V for Program, Erase and Read
s s
- VPP = 12V for fast Program (optional) MULTIPLEXED ADDRESS/DATA SYNCHRONOUS / ASYNCHRONOUS READ - Configurable Burst mode Read - Page mode Read (4 Words Page) - Random Access: 100ns
LFBGA54 (ZC) 10 x 4 ball array BGA46 (GC) 10 x 4 ball array
BGA
BGA
s
PROGRAMMING TIME - 10s by Word typical - Double Word Programming Option
s
MEMORY BLOCKS - Dual Bank Memory Array: 8 Mbit - 24 Mbit - Parameter Blocks (Top or Bottom location) Figure 1. Logic Diagram
s
DUAL BANK OPERATIONS - Read within one Bank while Program or Erase within the other - No delay between Read and Write operations
VDD VDDQ VPP 5 A16-A20 W E G RP WP L K M59MR032C M59MR032D BINV WAIT 16 ADQ0-ADQ15
s
BLOCK PROTECTION/UNPROTECTION - All Blocks protected at Power-up - Any combination of Blocks can be protected
s s s s
COMMON FLASH INTERFACE (CFI) 64 bit SECURITY CODE ERASE SUSPEND and RESUME MODES 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code, M59MR032C: A4h - Bottom Device Code, M59MR032D: A5h
s
VSS
AI90109
April 2001
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M59MR032C, M59MR032D
Figure 2. LFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
A
DU
DU
B
DU
DU
C
DU
DU
D
DU
DU
E
WAIT
VSS
K
VDD
W
VPP
A19
A17
F
VDDQ
A16
A20
L
BINV
RP
WP
A18
E
VSS
G
VSS
ADQ7
ADQ6
ADQ13
ADQ12
ADQ3
ADQ2
ADQ9
ADQ8
G
H
ADQ15
ADQ14
VSS
ADQ5
ADQ4
ADQ11
ADQ10
VDDQ
ADQ1
ADQ0
J
DU
DU
K
DU
DU
L
DU
DU
M
DU
DU
AI90110
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M59MR032C, M59MR032D
Figure 3. BGA Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
DU
DU
B
DU
DU
C
WAIT
VSS
K
VDD
W
VPP
A19
A17
D
VDDQ
A16
A20
L
BINV
RP
WP
A18
E
VSS
E
VSS
ADQ7
ADQ6
ADQ13
ADQ12
ADQ3
ADQ2
ADQ9
ADQ8
G
F
ADQ15
ADQ14
VSS
ADQ5
ADQ4
ADQ11
ADQ10
VDDQ
ADQ1
ADQ0
G
DU
DU
H
DU
DU
AI90111
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M59MR032C, M59MR032D
Table 1. Signal Names
A16-A20 ADQ0-ADQ15 E G W RP WP K L WAIT BINV VDD VDDQ VPP VSS DU Address Inputs Data Input/Outputs or Address Inputs, Command Inputs Chip Enable Output Enable Write Enable Reset/Power-down Write Protect Burst Clock Latch Enable Wait Data in Burst Mode Bus Invert Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Don't Use as Internally Connected
DESCRIPTION The M59MR032 is a 32 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-byWord basis using a 1.65V to 2.0V V DD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated internally. The device supports synchronous burst read and asynchronous page mode read from all the blocks of the memory array; at power-up the device is configured for page mode read. In synchronous burst mode, a new data is output at each clock cycle for frequencies up to 54MHz. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power-up. Blocks can be unprotected to make changes in the application and then reprotected. Instructions for Read/Reset, Auto Select, Write Configuration Register, Programming, Block Erase, Bank Erase, Erase Suspend, Erase Resume, Block Protect, Block Unprotect, Block Locking, CFI Query, are written to the memory through a Command Interface (C.I.) using standard microprocessor write timings. The memory is offered in LFBGA54 and BGA46, 0.5 mm ball pitch packages and it is supplied with all the bits erased (set to '1').
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO (3) VDD, VDDQ VPP Parameter Ambient Operating Temperature (2) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Value -40 to 85 -40 to 125 -55 to 155 -0.5 to VDDQ+0.5 -0.5 to 2.7 -0.5 to 13 Unit C C C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range. 3. Minimum Voltage may undershoot to -2V during transition and for less than 20ns.
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M59MR032C, M59MR032D
Organization The M59MR032 is organized as 2Mbit by 16 bits. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-A20 are the MSB addresses. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. The clock K input synchronizes the memory to the microprocessor during burst read. Reset RP is used to reset all the memory circuitry and to set the chip in power-down mode if this function is enabled by a proper setting of the Configuration Register. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on ADQ7 provides a Data Polling signal, ADQ6 and ADQ2 provide Toggle signals and ADQ5 provides error bit to indicate the state of the P/E.C operations. WAIT output indicates to the microprocessor the status of the memory during the burst mode operations. Memory Blocks The device features asymmetrically blocked architecture. M59MR032 has an array of 71 blocks and is divided into two banks A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible into Bank B or vice versa. The memory also features an erase suspend allowing to read or program in another block within the same bank. Once suspended the erase can be resumed. The Bank Size and Sectorization are summarized in Table 8. Parameter Blocks are located at the top of the memory address space for the M59MR032C, and at the bottom for the M59MR032D. The memory maps are shown in Tables 4, 5, 6 and 7. The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. Instructions are provided to protect or unprotect any block in the application. A second register locks the protection status while WP is low (see Block Locking description). All blocks are protected and unlocked at Power-up.
Table 3. Bank Size and Sectorization
Bank Size Bank A Bank B 8 Mbit 24 Mbit Parameter Blocks 8 blocks of 4 KWord Main Blocks 15 blocks of 32 KWord 48 blocks of 32 KWord
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M59MR032C, M59MR032D
Table 4. Bank A, Top Boot Block Addresses M59MR032C
# 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1FF000h-1FFFFFh 1FE000h-1FEFFFh 1FD000h-1FDFFFh 1FC000h-1FCFFFh 1FB000h-1FBFFFh 1FA000h-1FAFFFh 1F9000h-1F9FFFh 1F8000h-1F8FFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh
Table 5. Bank B, Top Boot Block Addresses M59MR032C
# 47 46 45 44 43 42 41 40 39 Size (KWord) 32 32 32 32 32 32 32 32 32 Address Range 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh
11 10 9 8 7 6 5 4 3 2 1 0
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Table 6. Bank B, Bottom Boot Block Addresses M59MR032D
# 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh # 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 32 32 32 32 32 32 32 32 32 32 32 32 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh
Table 7. Bank A, Bottom Boot Block Addresses M59MR032D
Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh
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M59MR032C, M59MR032D
SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs or Data Input/Output (ADQ0ADQ15). When Chip Enable E is at VIL and Output Enable G is at VIH the multiplexed address/ data bus is used to input addresses for the memory array, data to be programmed in the memory array or commands to be written to the C.I. The address inputs for the memory array are latched on the rising edge of Latch Enable L. The address latch is transparent when L is at VIL. Both input data and commands are latched on the rising edge of Write Enable W. When Chip Enable E and Output Enable G are at VIL the address/data bus outputs data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection status the Configuration Register status or the Status Register Data Polling bit ADQ7, the Toggle Bits ADQ6 and ADQ2, the Error bit ADQ5. The address/data bus is high impedance when the chip is deselected, Output Enable G is at VIH, or RP is at VIL. Address Inputs (A16-A20). The five MSB addresses of the memory array are latched on the rising edge of Latch Enable L. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at V IL. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is at VIH the outputs are High impedance. Write Enable (W). This input controls writing to the Command Register and Data latches. Data are latched on the rising edge of W. Write Protect (WP). This input gives an additional hardware protection level against program or erase when pulled at VIL, as described in the Block Lock instruction description. Reset/Power-down Input (RP). The RP input provides hardware reset of the memory, and/or Power-down functions, depending on the Configuration Register status. Reset/Power-down of the memory is achieved by pulling RP to VIL for at least tPLPH. When the reset pulse is given, if the memory is in Read, Erase Suspend Read or Standby, it will output new valid data in tPHQ7V1 after the rising edge of RP. If the memory is in Erase or Program modes, the operation will be aborted and the reset recovery will take a maximum of tPLQ7V. The memory will recover from Powerdown (when enabled) in tPHQ7V2 after the rising edge of RP. Exit from Reset/Power-down changes the contents of the configuration register bits 14 and 15, setting the memory in asynchronous page mode read and power save function disabled. All blocks are protected and unlocked after a Reset/ Power-down. See Tables 29, 31 and Figure 14. Latch Enable (L). L latches the address bits ADQ0-ADQ15 and A16-A20 on its rising edge. The address latch is transparent when L is at VIL and it is inhibited when L is at V IH. Clock (K). The clock input synchronizes the memory to the microcontroller during burst mode read operation; the address is latched on a K edge (rising or falling, according to the configuration settings) when L is at VIL. K is don't care during asynchronous page mode read and in write operations. Wait (WAIT). WAIT is an output signal used during burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. This output is high impedance when E or G are high or RP is at VIL, and can be configured to be active during the wait cycle or one clock cycle in advance.
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Bus Invert (BINV). BINV is an input/output signal used to reduce the amount of power needed to switch the external address/data bus. The power saving is achieved by inverting the data output on ADQ0-ADQ15 every time this gives an advantage in terms of number of toggling bits. In burst mode read, each new data output from the memory is compared with the previous data. If the number of transitions required on the data bus is in excess of 8, the data is inverted and the BINV signal will be driven by the memory at VOH to inform the receiving system that data must be inverted before any further processing. By doing so, the actual transitions on the data bus will be less than 8. In a similar way, when a command is given, BINV may be driven by the system at VIH to inform the memory that the data must be inverted.Like the other input/ output pins, BINV is high impedance when the chip is deselected, output enable G is at VIH or RP is at VIL; when used as an input, BINV must follow the same setup and hold timings of the data inputs. VDD and VDDQ Supply Voltage (1.65V to 2.0V). The main power supply for all operations (Read, Program and Erase). V DD and VDDQ must be at the same voltage. V PP Program Supply Voltage (12V). VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin; if VPP is kept in a low voltage range (0 to 2V) VPP is seen as a control input, and the current absorption is limited to 5A (0.2A typical). In this case with V PP = VIL we obtain an absolute protection against program or erase; with VPP = V PP1 these functions are enabled. VPP value is only sampled during program or erase write cycles; a change in its value after the operation has been started does not have any effect and program or erase are carried on regularly. If VPP is used in the 11.4V to 12.6V range (V PP2) then the pin acts as a power supply. This supply voltage must remain stable as long as program or erase are finished. In read mode the current sunk is less then 0.5mA, while during program and erase operations the current may increase up to 10mA. VSS Ground. VSS is the reference for all the voltage measurements.
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M59MR032C, M59MR032D
DEVICE OPERATIONS The following operations can be performed using the appropriate bus cycles: Address Latch, Read Array (Random, and Page Modes), Write command, Output Disable, Standby, Reset/Powerdown and Block Locking. See Table 8. Address Latch. In asynchronous operation, the address is latched on the rising edge of L input; in burst mode, the address is latched either by L going high or with a rising/falling edge of K, depending on the clock configuration. Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register, the CFI, the Block Protection Status, the Configuration Register status and the Security Code. Table 8. User Bus Operations (1)
Operation Write Output Disable Standby Reset / Power-down Block Locking
Note: 1. X = Don't care.
Read operation of the Memory Array may be performed in asynchronous page mode or synchronous burst mode. In asynchronous page mode data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by ADQ0 and ADQ1 address inputs. According to the device configuration the following Read operations: Electronic Signature - Status Register - CFI - Block Protection Status - Configuration Register Status - Security Code must be accessed as asynchronous read or as single synchronous burst mode (see Figure 4). Both Chip Enable E and Output Enable G must be at VIL in order to read the output of the memory.
E VIL VIL VIH X VIL
G VIH VIH X X X
W VIL VIH X X X
RP VIH VIH VIH VIL VIH
WP VIH VIH VIH VIH VIL
ADQ0-ADQ15 Data Input Hi-Z Hi-Z Hi-Z X
Table 9. Read Electronic Signature (AS and Read CFI instructions) (1)
Code Manufacturer Code M59MR032C Device Code M59MR032D VIL VIL VIH 01h Don't Care 00A5h
Note: 1. Addresses are latched on the rising edge of L input.
Device
E VIL VIL
G VIL VIL
W VIH VIH
A0-A7 00h 01h
A8-A20 Don't Care Don't Care
Data 0020h 00A4h
Table 10. Read Block Protection (AS and Read CFI instructions) (1)
Block Status Protected and unlocked Unprotected and unlocked Protected and locked Unprotected and locked (2) E VIL VIL VIL VIL G VIL VIL VIL VIL W VIH VIH VIH VIH A0-A7 02h 02h 02h 02h A8-A11 Don't Care Don't Care Don't Care Don't Care A12-A20 Block Address Block Address Block Address Block Address Data 0001 0000 0003 0002
Note: 1. Addresses are latched on the rising edge of L input. 2. A locked block can be unprotected only with WP at VIH.
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Figure 4. Read Operation Sequence when CR15 = 0 (excluding Read Memory Array)
K
L
A16-A20
VALID ADDRESS CONF. CODE 2
ADQ0-ADQ15
VALID ADDRESS
VALID DATA
NOT VALID
NOT VALID
CONFIGURATION CODE 3 ADQ0-ADQ15 VALID ADDRESS VALID DATA CONFIGURATION CODE 6 ADQ0-ADQ15 VALID ADDRESS VALID DATA NOT VALID
AI90112
Burst Read. The device also supports a burst read. In this mode, an address is first latched on the rising edge of L or K (or falling edge of K, according to configuration settings); after a configurable delay of 2 to 6 clock cycles a new data is output at each clock cycle. The burst sequence may be configured for linear or interleaved order and for a length of 4, 8 words or for continuous burst mode. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 32 word boundary and the starting address was at the end of a four word boundary. See the Write Configuration Register (CR) Instruction for more details on all the possible settings for the synchronous burst read. Write. Write operations are used to give Instruction Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E and Write Enable W are at V IL with Output Enable G at VIH. Addresses are latched on the rising edge of L. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Noise pulses of less than 5ns typical on E, W and G signals do not start a write cycle. Write operations are asynchronous and clock is ignored during write. Dual Bank Operations. The Dual Bank allows to read data from one bank of memory while a pro-
gram or erase operation is in progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in different banks without any delay. Status Register during Program or Erase must be monitored using an address within the bank being modified. Output Disable. The data outputs are high impedance when the Output Enable G is at VIH with Write Enable W at VIH. Standby. The memory is in standby when Chip Enable E is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. The automatic standby feature is not available when the device is configured for synchronous burst mode. Power-down. The memory is in Power-down when the Configuration Register is set for Powerdown and RP is at VIL. The power consumption is reduced to the Power-down level, and Outputs are in high impedance, independent of the Chip Enable E, Output Enable G or Write Enable W inputs. Block Locking. Any combination of blocks can be temporarily protected against Program or Erase by setting the lock register and pulling WP to VIL (see Block Lock instruction).
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INSTRUCTIONS AND COMMANDS Seventeen instructions are defined (see Table 17), and the internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits can be read at any time, during programming or erase, to monitor the progress of the operation. Instructions, made up of one or more commands written in cycles, can be given to the Program/ Erase Controller through a Command Interface (C.I.). The C.I. latches commands written to the memory. Commands are made of address and data sequences. Two Coded Cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The Coded Sequence consists of writing the data AAh at the address 555h during the first cycle and the data 55h at the address 2AAh during the second cycle. Instructions are composed of up to six cycles. The first two cycles input a Coded Sequence to the Command Interface which is common to all instructions (see Table 17). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature, Block Protection, Configuration Register Status or CFI Query for Read operations. In order to give additional data protection, the instructions for Block Erase and Bank Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For a Double Word Programming instruction, the fourth and fifth command cycles input the address and data to be programmed. For a Block Erase and Bank Erase instructions, the fourth and fifth cycles input a further Coded Sequence before the Erase confirm command on the sixth cycle. Any combination of blocks of the same memory bank can be erased. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied the command interface is reset to Read Array. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to ensure maximum data security. Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded Cycles. Subsequent read operations will read the memory array addressed and output the data read. The Reset command does not affect the configuration of unprotected blocks and the Configuration Register status. Read/Reset Instruction is ignored when program or erase is in progress. CFI Query (RCFI) Instruction. Common Flash Interface Query mode is entered writing 98h at address 55h. The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Tables 19, 20, 21 and 22 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number, organized by word, is written starting at address 81h. This area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by ST. Write a read instruction (RD) to return to Read Array mode. Table 11. Commands
Hex Code 00h 10h 20h 30h 40h Bypass Reset Bank Erase Confirm Unlock Bypass Block Erase Resume/Confirm Double Word Program Block Protect, or Block Unprotect, or Block Lock, or Write Configuration Register Set-up Erase Read Electronic Signature, or Block Protection Status, or Configuration Register Status CFI Query Program Erase Suspend Read Array/Reset Command
60h
80h 90h 98h A0h B0h F0h
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Auto Select (AS) Instruction. This instruction uses two Coded Cycles followed by one write cycle giving the command 90h to address 555h for command set-up. A subsequent read will output the Manufacturer or the Device Code (Electronic Signature), the Block Protection status or the Configuration Register status depending on the levels of ADQ0 and ADQ1 (see Tables 9, 10 and 11). The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of M59MR032. The Manufacturer Code is output when the address lines ADQ0 and ADQ1 are at VIL, the Device Code is output when ADQ0 is at VIH with ADQ1 at V IL. The codes are output on ADQ0-ADQ7 with ADQ8ADQ15 at 00h. The AS instruction also allows the access to the Block Protection Status. After giving the AS instruction, ADQ0 is set to VIL with ADQ1 at VIH, while A12-A20 define the address of the block to be verified (see Table 10). The AS Instruction finally allows the access to the Configuration Register status if both ADQ0 and ADQ1 are set to VIH; refer to Table 12 for configuration register description. A reset command puts the device in Read Array mode. Write Configuration Register (CR) Instruction. This instruction uses two Coded Cycles followed by one write cycle giving the command 60h to address 555h. A further write cycle giving the command 03h writes the contents of address bits ADQ0-ADQ15 to bits CR15-CR0 of the configuration register. At Power-up the Configuration Register is set to asynchronous Read mode, Powerdown disabled and bus invert (power save function) disabled. A description of the effects of each configuration bit is given in Table 12.
Table 12. Read Configuration Register (AS and Read CFI instructions)
Configuration Register CR15 Function Read mode 0 = Burst mode read 1 = Page mode read (default) Bus Invert configuration (power save) 0 = disabled (default) 1 = enabled X-Latency 010 = 2 clock latency 011 = 3 clock latency 100 = 4 clock latency 101 = 5 clock latency 110 = 6 clock latency Power-down configuration 0 = power-down disabled (default) 1 = power-down enabled Data hold configuration 0 = data output at every clock cycle 1 = data output every 2 clock cycles Wait configuration 0 = WAIT is active during wait state 1 = WAIT is active one data cycle before wait state Burst order configuration 0 = Interleaved 1 = Linear Clock configuration 0 = Address latched and data output on the falling clock edge. 1 = Address latched and data output on the rising clock edge. Reserved Burst length 001 = 4 word burst length 010 = 8 word burst length 111 = Continuous burst mode (requires CR7 = 1)
CR14
CR13-CR11
CR10
CR9
CR8
CR7
CR6 CR5-CR3
CR2-CR0
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M59MR032C, M59MR032D
Table 13. X-Latency Configuration
Configuration Code 2 3 4 5 (1) 6 (1) Input Frequency 100ns 25MHz 40MHz 54MHz 66MHz - 120ns 20MHz 30MHz 40MHz 50MHz 60MHz
Note: 1. Configuration codes 5 and 6 may be used only in conjunction with configuration bit CR9 set at "1" (one data every 2 clock cycles).
Figure 5. X-Latency Configuration Sequence
K
L
A16-A20
VALID ADDRESS CONF. CODE 2
ADQ0-ADQ15
VALID ADDRESS
VALID DATA VALID DATA
VALID DATA
CONFIGURATION CODE 3 ADQ0-ADQ15 VALID ADDRESS VALID DATA CONFIGURATION CODE 6 ADQ0-ADQ15 VALID ADDRESS VALID DATA VALID DATA
AI90113
- Read mode (CR15). The device supports an asynchronous page mode and a synchronous burst mode. In asynchronous page mode, the default at power-up, data is internally read and stored in a buffer of 4 words selected by ADQ0 and ADQ1 address inputs. In synchronous burst mode, the device latches the starting address and then outputs a sequence of data which depends on the configuration register settings. - Bus Invert configuration (CR14). This register bit is used to enable the BINV pin functionality. BINV functionality depends upon configuration bits CR14 and CR15 (see Table 12 for configuration bits definition) as shown in Table 14.
As output pin BINV is active only when enabled (CR14 = 1) in Read Array burst mode (CR15 = 0). As input pin BINV is active only when enabled (CR14 = 1). BINV is ignored when ADQ0ADQ15 lines are used as address inputs (addresses must not be inverted). Table 14. BINV Configuration Bits
CR15 0 0 1 1 CR14 0 1 0 1 BINV IN X Active X Active OUT 0 Active 0 0
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Table 15. Burst Order and Length Configuration
Starting Address 0 1 2 3 ... 7 ... 28 29 30 31 28-29-30-31-32... 29-30-31-WAIT-32... 30-31-WAIT-WAIT-32... 31-WAIT-WAIT-WAIT-32... 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11... 4 Words Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 8 Words Continuous Burst Interleaved 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 0-1-2-3-4-5... 1-2-3-4-5-6... 2-3-4-5-6-7... 3-4-5-6-7-8...
- X-Latency (CR13-CR11). These configuration bits define the number of clock cycles elapsing from L going low to valid data available in burst mode. The correspondence between X-Latency settings and the sustainable clock frequencies is given in Table 13 and Figure 5. - Power-down configuration (CR10). The RP pin may be configured to give a very low power consumption when driven low (power-down state). In power-down the ICC supply current is reduced to a typical figure of 2A; if this function is disabled (default at power-up) the RP pin causes only a reset of the device and the supply current is the stand-by value. The recovery time after a RP pulse is significantly longer (50s vs. 150ns) when power-down is enabled. - Data hold configuration (CR9). In burst mode this register bit determines if a new data is output at each clock cycle or every 2 clock cycles. - Wait configuration (CR8). In burst mode WAIT indicates whether the data on the output bus are valid or a wait state must be inserted. The configuration bit determines if WAIT will be asserted one clock cycle before the wait state or during the wait state (see Figure 10). - Burst order configuration (CR7). See Table 15 for burst order and length. - Clock configuration (CR6). In burst mode determines if address is latched and data is output on the rising or falling edge of the clock. - Burst length (CR2-CR0). In burst mode determines the number of words output by the memory. It is possible to have 4 words, 8 words or a
continuous burst mode, in which all the words in bank A or bank B are read sequentially. In continuous burst mode the burst sequence is interrupted at the end of each of the two banks or when a suspended block is reached. In continuous burst mode it may happen that the memory will stop the data output flow for a few clock cycles; this event is signaled by WAIT going low until the output flow is resumed. The initial address determines if the output delay will occur as well as its duration. If the starting address is aligned to a four word boundary no wait states will be needed. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1,2 or 3 clock cycles (2,4, 6 cycles if CR9 is set at "1") when the burst sequence is crossing the first 32 word boundary. WAIT will be asserted only once during a continuous burst access. See also Table 15. Enter Bypass Mode (EBY) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 20h to address 555h for mode set-up. Once in Bypass mode, the device will accept the Exit Bypass (XBY) and Program or Double Word Program in Bypass mode (PGBY, DPGBY) commands. The Bypass mode allows to reduce the overall programming time when large memory arrays need to be programmed. Exit Bypass Mode (XBY) Instruction. This instruction uses two write cycles. The first inputs to the memory the command 90h and the second inputs the Exit Bypass mode confirm (00h). After the XBY instruction, the device resets to Read Memory Array mode.
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Table 16. Protection States (1)
Current State (2) (WP, ADQ1, ADQ0) 100 101 110 111 000 001 011 Program/Erase Allowed yes no yes no yes no no Next State After Event (3) Protect 101 101 111 111 001 001 011 Unprotect 100 100 110 110 000 000 011 Lock 111 111 111 111 011 011 011 WP transition 000 001 011 011 100 101 111 or 110 (4)
Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status. 2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by ADQ1 (= 1 for a locked block) and ADQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = V IH and A0 = VIL. 3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed its logic value. 4. A WP transition to VIH on a locked block will restore the previous ADQ0 value, giving a 111 or 110.
Program in Bypass Mode (PGBY) Instruction. This instruction uses two write cycles. The Program command A0h is written to any Address on the first cycle and the second write cycle latches the Address on the rising edge of L and the Data to be written on the rising edge of W and starts the P/E.C. Read operations within the same bank output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. The content of the memory cell is not changed if the user write '1' in place of '0' and no error occurs. Status bits ADQ6 and ADQ7 determine if programming is ongoing and ADQ5 allows verification of any possible error. Program (PG) Instruction. This instruction uses four write cycles. The Program command A0h is written to address 555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Data to be written and starts the P/E.C. Read operations within the same bank output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. The content of the memory cell is not changed if the user write '1' in place of '0' and no error occurs. Status bits ADQ6 and ADQ7 determine if programming is on-going and ADQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend. Double Word Program (DPG) Instruction. This feature is offered to improve the programming throughput, writing a page of two adjacent words
in parallel. High voltage (11.4V to 12.6V) on VPP pin is required. This instruction uses five write cycles. The double word program command 40h is written to address 555h on the third cycle after two Coded Cycles. A fourth write cycle latches the address and data to be written to the first location. A fifth write cycle latches the new data to be written to the second location and starts the P/E.C.. Note that the two locations must have the same address except for the address bit A0. The Double Word Program can be executed in Bypass mode (DPGBY) to skip the two coded cycles at the beginning of each command. Block Protect (BP), Block Unprotect (BU), Block Lock (BL) Instructions. All blocks are protected and unlocked at power-up. Each block of the array has two levels of protection against program or erase operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WP pin, according to the following scheme: - when WP is at V IH, the Lock status is overridden and all blocks can be protected or unprotected; - when WP is at V IL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status, and program or erase accordingly;
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- the lock status is cleared for all blocks at powerup or pulling RP at VIL for at least tPLPH. The protection and lock status can be monitored for each block using the Autoselect (AS) instruction. Protected blocks will output a `1' on ADQ0 and locked blocks will output a `1' on ADQ1. After a pulse of RP of at least tPLPH all blocks are protected and unlocked. Refer to Table 16 for a list of the protection states. Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles and an address within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. All blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. The erase will start after an erase timeout period of 100s. Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of ADQ3, if ADQ3 is '0' the Block Erase Command has been given and the timeout is running, if ADQ3 is '1', the timeout has expired and the P/ E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read operations within the same bank, after the sixth rising edge of W or E, output the status register bits. During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES instruction; the Read/Reset RD instruction is accepted during the 100s time-out period. Data Polling bit ADQ7 returns '0' while the erasure is in progress and '1' when it has completed. The Toggle bit ADQ6 toggles during the erase operation, and stops when erase is completed. After completion the Status Register bit ADQ5 returns '1' if there has been an erase failure. In such a situation, the Toggle bit ADQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C. Bank Erase (BKE) Instruction. This instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. The Erase Set-up command 80h is written to address 555h on the third cycle after the two Coded cycles. The Bank Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles at an address within the selected bank. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations within the same bank after the sixth rising edge of W or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit ADQ7 returns '0', then '1' on completion. The Toggle bit ADQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit ADQ5 returns '1' if there has been an Erase Failure. Erase Suspend (ES) Instruction. In a dual bank memory the Erase Suspend instruction is used to read data within the bank where erase is in progress. It is also possible to program data in blocks not being erased. The Erase Suspend instruction consists of writing the command B0h without any specific address. No Coded Cycles are required. Erase suspend is accepted only during the Block Erase instruction execution. The Toggle bit ADQ6 stops toggling when the P/E.C. is suspended within 15s after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output ADQ2 toggling and ADQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instructions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in ADQ6 toggling when the data is being programmed. Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank being erased and without any Coded Cycle.
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Table 17. Instructions (1,2)
Mne. Instr. Cyc. 1+ RD (4) Read/Reset Memory Array 3+ Data Addr. RCFI CFI Query 1+ Data Addr. AS
(4)
1st Cyc. Addr. (3) Data Addr. X
2nd Cyc.
3rd Cyc.
4th Cyc.
5th Cyc.
6th Cyc.
Read Memory Array until a new write cycle is initiated. F0h 555h AAh 55h Read CFI data until a new write cycle is initiated. 98h 555h AAh 555h AAh 555h AAh 555h AAh 555h AAh X 90h X A0h X 40h 555h AAh 555h AAh 2AAh 55h 2AAh 55h 2AAh 55h 2AAh 55h 2AAh 55h X 00h Program Address Read Data Polling or Toggle Bit until Program Program completes. Data Program Program Address 1 Address 2 Note 6, 7 Program Data 1 2AAh 55h 2AAh 55h Program Data 2 555h 60h 555h 60h Block Address 01h Block Address D0h 555h 90h 555h 60h 555h A0h 555h 40h 555h 20h Read electronic Signature or Block Protection or Configuration Register Status until a new cycle is initiated. Configuration Data 03h Program Address Read Data Polling or Toggle Bit until Program Program completes. Data Program Program Address 1 Address 2 Note 6, 7 Program Data 1 Program Data 2 2AAh 55h 555h F0h Read Memory Array until a new write cycle is initiated.
Auto Select
3+ Data Addr. 4 Data Addr.
CR
Configuration Register Write
PG
Program
4 Data Addr.
DPG
Double Word Program
5 Data
EBY
Enter Bypass Mode Exit Bypass Mode
Addr. 3 Data Addr. 2 Data Addr.
XBY
PGBY
Program in Bypass Mode
2 Data Addr. 3 Data Addr.
Double Word DPGBY Program in Bypass Mode
BP
Block Protect
4 Data Addr.
BU
Block Unprotect
1 Data
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Mne. Instr. Cyc. Addr. BL Block Lock 4 Data Addr. BE Block Erase 6+ Data Addr. BKE Bank Erase 6 Data ES Erase Suspend 1 Addr. (3) Data Addr. ER
Note: 1. 2. 3. 4.
1st Cyc. 555h AAh 555h AAh 555h AAh X B0h Bank Address 30h
2nd Cyc. 2AAh 55h 2AAh 55h 2AAh 55h
3rd Cyc. 555h 60h 555h 80h 555h 80h
4th Cyc. Block Address 2Fh 555h AAh 555h AAh
5th Cyc.
6th Cyc.
2AAh 55h 2AAh 55h
Block Address 30h Bank Address 10h
Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase.
Erase Resume
1 Data
Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time
Commands not interpreted in this table will default to read array mode. For Coded cycles address inputs A11-A20 are don't care. X = Don't Care. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles. 5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0. 7. High voltage on VPP (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction.
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STATUS REGISTER BITS P/E.C. status is indicated during execution by Data Polling on ADQ7, detection of Toggle on ADQ6 and ADQ2, or Error on ADQ5 bits. Any read attempt within the Bank being modified and during Program or Erase command execution will automatically output these five Status Register bits. The P/E.C. automatically sets bits ADQ2, ADQ5, ADQ6 and ADQ7. Other bits (ADQ0, ADQ1 and ADQ4) are reserved for future use and should be masked (see Table 18). Read attempts within the bank not being modified will output array data. Toggle bits ADQ6 and ADQ2 are affected by G and/or E cycles regardless of the bank in which these cycles refer to. This means that toggle bits are in a state that depends on the amount of accesses to both banks and not only to the bank where erasing or programming is on going. Status Register Bits must be accessed according to the device configuration (see Figure 4). Data Polling Bit (ADQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on ADQ7. In case of a double word program operation, the complement is done on ADQ7 of the last word written to the command interface, i.e. the data written in the fifth cycle. During Erase operation, it outputs a '0'. After completion of the operation, ADQ7 will output the bit last programmed or a '1' after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be performed at the address being programmed or at an address within the block being erased. See Figure 17 for the Data Polling flowchart and Figure 15 for the Data Polling waveforms. ADQ7 will also flag the Erase Suspend mode by switching from '0' to '1' at the start of the Erase Suspend. In order to monitor ADQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Suspend mode, ADQ7 will output '1' if the read is attempted on a block being erased and the data value on other blocks. During Program operation in Erase Suspend Mode, ADQ7 will have the same behavior as in the normal program execution outside of the suspend mode. Toggle Bit (ADQ6). When Programming or Erasing operations are in progress, successive attempts to read ADQ6 will output complementary data. ADQ6 will toggle following toggling of either G, or E when G is at VIL. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a '1' after erasing. The toggle bit ADQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. ADQ6 will be set to '1' if a Read operation is attempted on an Erase Suspend block. When erase is suspended ADQ6 will toggle during programming operations in a block different from the block in Erase Suspend. Either E or G toggling will cause ADQ6 to toggle. See Figure 18 for Toggle Bit flowchart and Figure 16 for Toggle Bit waveforms. Toggle Bit (ADQ2). This toggle bit, together with ADQ6, can be used to determine the device status during the Erase operations. During Erase Suspend a read from a block being erased will cause ADQ2 to toggle. A read from a block not being erased will output data. ADQ2 will be set to '1' during program operation. After erase completion and if the error bit ADQ5 is set to '1', ADQ2 will toggle if the faulty block is addressed. Error Bit (ADQ5). This bit is set to '1' by the P/ E.C. when there is a failure of programming or block erase, that results in invalid data in the memory block. In case of an error in block erase or program, the block in which the error occurred or to which the programmed data belongs, must be discarded. Other Blocks may still be used. The error bit resets after a Read/Reset (RD) instruction. In case of success of Program or Erase, the error bit will be set to '0'. Erase Timer Bit (ADQ3). This bit is set to `0' by the P/E.C. when the last block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, ADQ3 returns to `1', in the range of 80s to 120s.
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Table 18. Status Register Bits (1)
Status Program Block Erase Timeout Block/Chip Erase In Progress Erase Suspend Mode Erase Suspended Block Non Erase Suspended Block DQ7 1 1 0 N/A Toggle Automatic return to reading array data Toggle 0 N/A 1 DQ7 (2) DQ7 0 0 DQ6 Toggle Toggle Toggle DQ5 0 0 0 DQ3 N/A 0 1 DQ2 (2) 1 N/A N/A
Programming during Erase Suspend Successfully/ Completed Word Program
Automatic return to reading array data Block/Chip Erase Word Program DQ7 0 DQ7 Toggle Toggle Toggle 1 1 1 N/A 1 N/A 1 Toggle is failed, block is addressed 1
Exceeded Time Limit
Block/Chip Erase Program in Suspend
Note: 1. Status Register bits do not consider BINV. 2. DQ7 and DQ2 require a valid address when reading status information.
POWER CONSUMPTION Power-down The memory provides Reset/Power-down control input RP. The Power-down function can be activated only if the relevant Configuration Register bit is set to '1'. In this case, when the RP signal is pulled at V SS the supply current drops to typically ICC2 (see Table 28), the memory is deselected and the outputs are in high impedance.If RP is pulled to VSS during a Program or Erase operation, this operation is aborted in tPLQ7V and the memory content is no longer valid (see Reset/Power-down input description).
Power-up The memory Command Interface is reset on Power-up to Read Array. Either E or W must be tied to VIH during Power-up to allow maximum security and the possibility to write a command on the first rising edge of W. At Power-up the device is configured as: - page mode: (CR15 = 1) - power-down disabled: (CR10 = 0) - BINV disabled: (CR14 = 0) and all blocks are protected and unlocked. Supply Rails Normal precautions must be taken for supply voltage decoupling; each device in a system should have the V DD rails decoupled with a 0.1F capacitor close to the VDD, VDDQ and VSS pins. The PCB trace widths should be sufficient to carry the required VDD program and erase currents.
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COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification is a JEDEC approved, standardised data structure that can be read from the Flash memory device. CFI allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. CFI allows the system to easily interface to the Flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. Tables 19, 20, 21, 22, 23 and 24 show the address used to retrieve each data. Table 19. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional)
The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Tables 19, 20, 21 and 22 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 81h. This area can be accessed only in read mode and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode. Refer to the CFI Query instruction to understand how the M59MR032 enters the CFI Query mode.
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 20, 21 and 22. Query data are always presented on the lowest order data outputs.
Table 20. CFI Query Identification String
Offset 00h 01h 02h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0020h 00A4h - Top 00A5h - Bottom reserved 0051h 0052h 0059h 0002h 0000h offset = P = 0039h Address for Primary Algorithm extended Query table 0000h 0000h 0000h value = A = 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Query Unique ASCII String "QRY" Manufacturer Code Device Code Reserved Description
Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are `0'.
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Table 21. CFI Query System Interface Information
Offset 1Bh Data 0017h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPP pin is present VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPP pin is present Typical timeout per single byte/word program (multi-byte program count = 1), 2n s (if supported; 0000h = not supported) Typical timeout for maximum-size multi-byte program or page write, 2n s (if supported; 0000h = not supported) Typical timeout per individual block erase, 2n ms (if supported; 0000h = not supported) Typical timeout for full chip erase, 2n ms (if supported; 0000h = not supported) Maximum timeout for byte/word program, 2n times typical (offset 1Fh) (0000h = not supported) Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h) (0000h = not supported) Maximum timeout per individual block erase, 2n times typical (offset 21h) (0000h = not supported) Maximum timeout for chip erase, 2n times typical (offset 22h) (0000h = not supported)
1Ch
0022h
1Dh
0017h
1Eh
00C0h
1Fh 20h 21h 22h 23h 24h 25h 26h
0004h 0004h 000Ah 0000h 0004h 0004h 0004h 0000h
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Table 22. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch Data 0016h 0001h 0000h 0000h 0000h 0003h Device Size = 2n in number of bytes Flash Device Interface Code description: Asynchronous x16 Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within device bit 7 to 0 = x = number of Erase Block Regions Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. For example, a 128KB device (1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered to have 5 Erase Block Regions. Even though two regions both contain 16KB blocks, the fact that they are not contiguous means they are separate Erase Block Regions. 3. By definition, symmetrically block devices have only one blocking region. M59MR032C 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h M59MR032D 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h M59MR032C 002Fh 0000h 0000h 0001h 000Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h M59MR032D 0007h 0000h 0020h 0000h 000Eh 0000h 0000h 0001h 002Fh 0000h 0000h 0001h Erase Block Region Information bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in size. The value z = 0 is used for 128 byte block size. e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase Block Region: e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") Note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 Description
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Table 23. Primary Algorithm-Specific Extended Query Table
Offset (P)h = 39h Data 0050h 0052h 0049h (P+3)h = 3Ch (P+4)h = 3Dh (P+5)h = 3Eh 0031h 0030h 00F2h 0003h (P+7)h (P+8)h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm bit 10-31 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. Chip Erase supported (1 = Yes, 0 = No) Suspend Erase supported (1 = Yes, 0 = No) Suspend Program supported (1 = Yes, 0 = No) Legacy Lock/Unlock supported (1 = Yes, 0 = No) Queued Erase supported (1 = Yes, 0 = No) Instant individual block locking supported (1 = Yes, 0 = No) Protection bits supported (1 = Yes, 0 = No) Page-mode read supported (1 = Yes, 0 = No) Synchronous read supported (1 = Yes, 0 = No) Simultaneous operation supported (1 = Yes, 0 = No) Primary Algorithm extended Query table unique ASCII string "PRI" Description
(P+9)h = 42h
0001h
Supported Functions after Suspend Read Array, Read Status Register and CFI Query bit 0 bit 7 to 1 Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0'
(P+A)h = 43h (P+B)h
0003h 0000h
Block Protect Status Defines which bits in the Block Protect Status Register section of the Query are implemented. Block Protect Status Register Protect/Unprotect bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' bit 0
(P+C)h = 45h
0018h
VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
(P+D)h = 46h
00C0h
VPP Supply Optimum Program/Erase voltage bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
(P+E)h = 47h
0000h
Reserved
25/49
M59MR032C, M59MR032D
Table 24. Burst Read Information
Offset (P+F)h = 48h Data 0003h Page-mode read capability bits 0-7 'n' such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine pagemode data output width. 00h indicates no read page buffer. Description
(P+10)h = 49h (P+11)h = 4Ah
0003h 0001h
Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Synchronous mode read capability configuration 1 bit 3-7 bit 0-2 Reserved 'n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width.
(P+12)h = 4Bh (P+13)h = 4Ch (P+14)h = 4Dh (P+15)h = 4Eh
0002h 0007h 0036h 0001h
Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Max operating clock frequency (MHz) Supported handshaking signal (WAIT pin) bit 0 bit 1 during synchronous read during asynchronous read (1 = Yes, 0 = No) (1 = Yes, 0 = No)
Table 25. Security Code Area
Offset 81h 82h 83h 84h Data XXXX XXXX XXXX XXXX 64 bits: unique device number Description
26/49
M59MR032C, M59MR032D
Table 26. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 4ns 0 to VDDQ VDDQ/2
1N914
Figure 7. AC Testing Load Circuit
VDDQ / 2
3.3k
Figure 6. Testing Input/Output Waveforms
DEVICE UNDER TEST CL = 30pF VDDQ/2 0V
AI90114
OUT
VDDQ
CL includes JIG capacitance
AI90115
Table 27. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
27/49
M59MR032C, M59MR032D
Table 28. DC Characteristics (TA = -40 to 85C; V DD = VDDQ = 1.65V to 2.0V)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current (Asynchronous Read Mode) ICC1 Supply Current (Synchronous Read Mode Continuous Burst) Supply Current (Power-down) Supply Current (Standby) Supply Current (Program or Erase) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH, f = 6MHz 10 Min Typ Max 1 5 20 Unit A A mA
E = VIL, G = VIH, f = 40MHz
20
30
mA
ICC2 ICC3 ICC4 (1)
RP = VSS 0.2V E = VDD 0.2V Word Program, Block Erase in progress Program/Erase in progress in one Bank, Asynchronous Read in the other Bank Program/Erase in progress in one Bank, Synchronous Read in the other Bank VPP = 12V 0.6V VPP VCC VPP = 12V 0.6V -0.5 VDDQ -0.4 IOL = 100A IOH = -100A Program, Erase Double Word Program VDDQ -0.1 VDDQ -0.4 11.4
2 15 10
10 50 20
A A mA
20
40
mA
ICC5 (1)
Supply Current (Dual Bank)
30
50
mA
IPP1
VPP Supply Current (Program or Erase) VPP Supply Current (Standby or Read) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CMOS VPP Supply Voltage VPP Supply Voltage
5 0.2 100
10 5 400 0.4 VDDQ + 0.4 0.1
mA A A V V V V
IPP2 VIL VIH VOL VOH VPP1 VPP2
VDDQ + 0.4 12.6
V V
Note: 1. Sampled only, not 100% tested. 2. VPP may be connected to 12V power supply for a total of less than 100 hrs.
28/49
M59MR032C, M59MR032D
Table 29. Asynchronous Read AC Characteristics (TA = -40 to 85C; VDD = VDDQ = 1.65V to 2.0V)
M59MR032 Symbol Alt Parameter Test Condition Min tAVAV tAVLH tAVQV tAVQV1 tEHQX tEHQZ (1) tELLH tELQV (2) tELQX (1) tGHQX tGHQZ (1) tGLQV (2) tGLQX (1) tLHAX tLHGL tLLLH tLLQV tLLQV1 tAVDLAVDH tAVDLQV tRC tAVAVDH tACC tPAGE tOH tHZ tELAVDH tCE tLZ tOH tDF tOE tOLZ tAVDHAX Address Valid to Next Address Valid Address valid to Latch Enable High Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width Latch Enable Low to Output Valid (Random) Latch Enable Low to Output Valid (Page) E = VIL, G = VIL G = VIH E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL, G = VIH G = VIL G = VIL E = VIL E = VIL E = VIL E = VIL E = VIL, G = VIH E = VIL E = VIL, G = VIH E = VIL E = VIL 0 10 10 10 100 45 0 0 20 25 0 10 10 10 120 45 10 100 0 0 20 35 0 20 10 120 100 10 100 45 0 20 100 Max Min 120 10 120 45 120 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV .
29/49
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tAVAV VALID ADDRESS tAVQV VALID ADDRESS tAVLH tLHAX VALID ADDRESS VALID DATA VALID ADDRESS tLLLH tLLQV tELLH tELQV tEHQZ tELQX tEHQX tGLQV tLHGL tGLQX tGHQX tGHQZ
AI90116
M59MR032C, M59MR032D
ADQ0-ADQ15
A16-A20
Figure 8. Asynchronous Read AC Waveforms
L
E
G
Note: Write Enable (W) = High.
ADQ0-ADQ15
VALID DATA VALID ADDRESS VALID DATA VALID ADDRESS VALID DATA VALID ADDRESS
VALID ADDRESS
VALID DATA
Figure 9. Page Read AC Waveforms
tAVLH VALID ADDRESS tLLQV1
tLHAX
tAVQV1
A16-A20
tLLQV
L
tELQV
E tGLQV
G tLHGL tGHQZ
AI90117
M59MR032C, M59MR032D
31/49
M59MR032C, M59MR032D
Table 30. Synchronous Burst Read AC Characteristics (TA = -40 to 85C; VDD = VDDQ = 1.65V to 2.0V)
M59MR032 Symbol Alt Parameter Test Condition Min tAVK tELK tK tKAX tKHKL tKLKH tKRV tKRX tKQV tKQX tLLK tAVCLKH tCELCLKH tCLK tCLKHAX tCLKHCLKL tCLKLCLKH tRLCLKH tCLKHRX tCLKHQV tCLKHQX tAVDLCLKH Address Valid to Clock Chip Enable Low to Clock Clock Period Clock to Address Transition Clock High Clock Low Clock to Wait Valid Clock to Wait Transition Clock to Data Valid Clock to Output Transition Latch Enable Low to Clock E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL E = VIL 4 7 4 14 4 7 E = VIL, G = VIH 7 7 15 10 5 5 14 4 18 100 Max Min 7 7 16 10 5 5 18 120 Max ns ns ns ns ns ns ns ns ns ns ns Unit
32/49
ADQ0-ADQ15 VALID D. VALID D. VALID D. VALID DATA
VALID ADDRESS
A16-A20 tLHAX
VALID ADDRESS
tAVLH
L tKQV tKQX tEHQX tEHQZ note 1 tKAX
tLLK
Figure 10. Synchronous Burst Read
tAVK
K
tELK
E tGLQX tGHQX tGHQZ
tLHGL
G
BINV
VALID
VALID tKRV note 2 note 3
VALID tKRV
WAIT
M59MR032C, M59MR032D
Note: 1. The number of clock cycles to be inserted depends upon the x-latency set in the read configuration register. 2. WAIT signal can be configured to be active during wait state or one cycle below wait state. 3. WAIT signal is asserted only when burst length is configured as continuous (see Burst Read section for further information).
AI90118
33/49
34/49
VALID DATA VALID DATA VALID VALID VALID note 1 note 2
AI90119
ADQ0-ADQ15
VALID DATA
A16-A20
M59MR032C, M59MR032D
L
K
E
G
BINV
Figure 11. Synchronous Burst Read (with Data Hold Configuration bit CR9 = 1)
WAIT
Note: 1. WAIT signal can be configured to be active during wait state or one cycle below wait state. 2. WAIT signal is asserted only when burst length is configured as continuous (see Burst Read section for further information).
M59MR032C, M59MR032D
Table 31. Write AC Characteristics, Write Enable Controlled (TA = -40 to 85 C; VDD = V DDQ = 1.65V to 2.0V)
M59MR032 Symbol Alt Parameter Min tAVAV tAVLH tDVWH tELLH tELWL tGHLL tGHWL tLHAX tLHWH tLLLH tPLQ7V tVDHEL tVPPHWH tWHDX tWHEH tWHGL tWHLL tWHVPPL tWHWL tWHWPL tWLWH tWPHWH tWP tWPH tDH tCH tOEH tVCS tCS tDS tWC Address Valid to Next Address Valid Address Valid to Latch Enable High Input Valid to Write Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Write Enable Low Output Enable High to Latch Enable Low Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable High to Write Enable High Latch Enable Pulse Width RP Low to Reset Complete During Program/Erase VDD High to Chip Enable Low VPP High to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Write Enable High to Latch Enable Low Write Enable High to VPP Low Write Enable High to Write Enable Low Write Enable High to Write Protect Low Write Enable Low to Write Enable High Write Protect High to Write Enable High 50 200 0 0 0 0 200 30 200 50 200 100 10 50 10 0 20 20 10 10 10 15 50 200 0 0 0 0 200 30 200 50 200 100 Max Min 120 10 50 10 0 20 20 10 10 10 15 120 Max ns ns ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns Unit
35/49
36/49
tAVAV ADDRESS VALID DATA VALID ADDRESS VALID tAVLH VALID tLLLH tLHWH tWHLL tLHAX tDVWH tWHDX tWLWH tELLH tELWL tWHGL tGHLL tGHWL tWPHWH tWHWPL tVPPHWH VPP2 VPP1 tWHVPPL
AI90120
ADQ0-ADQ15
A16-A20
M59MR032C, M59MR032D
BINV
L
Figure 12. Write AC Waveforms, W Controlled
W
E
G
WP
tVDHEL
VPP
VDD
M59MR032C, M59MR032D
Table 32. Write AC Characteristics, Chip Enable Controlled (TA = -40 to 85 C; VDD = V DDQ = 1.65V to 2.0V)
M59MR032 Symbol Alt Parameter Min tAVAV tAVLH tDVEH tEHDX tEHEL tEHWH tELEH tELLH tGHLL tLHAX tLHEH tLLLH tPLQ7V tVDHWL tVPPHEH tEHVPPL tEHWPL tWLEL tWPHEH tWS tVCS tDS tDH tCPH tWH tCP tWC Address Valid to Next Address Valid Address Valid to Latch Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Output Enable High to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Chip Enable High Latch Enable Pulse Width RP Low to Reset Complete During Program/Erase VDD High to Write Enable Low VPP High to Chip Enable High Chip Enable High to VPP Low Chip Enable High to Write Protect Low Write Enable Low to Chip Enable Low Write Protect High to Chip Enable High 50 200 200 200 0 200 100 10 50 0 30 0 70 10 20 10 10 10 15 50 200 200 200 0 200 100 Max Min 120 10 50 0 30 0 70 10 20 10 10 10 15 120 Max ns ns ns ns ns ns ns ns ns ns ns ns s s ns ns ns ns ns Unit
37/49
38/49
tAVAV ADDRESS VALID DATA VALID ADDRESS VALID tAVLH VALID tLLLH tLHEH tLHAX tDVEH tEHDX tEHWH tELLH tELEH tEHEL tGHLL tWPHEH tEHWPL tVPPHEH VPP2 VPP1 tEHVPPL
AI90121
ADQ0-ADQ15
A16-A20
M59MR032C, M59MR032D
BINV
L
tWLEL
Figure 13. Write AC Waveforms, E Controlled
W
E
G
WP
tVDHWL
VPP
VDD
M59MR032C, M59MR032D
Table 33. Read and Write AC Characteristic, RP Related (TA = -40 to 85C; VDD = VDDQ = 1.65V to 2.0V)
M59MR032 Symbol Alt Parameter Test Condition Min tPHQ7V1 tPHQ7V2 tPLPH tPLQ7V tRP RP High to Data Valid (Read Mode) RP High to Data Valid (Power-down enabled) RP Pulse Width RP Low to Reset Complete During Program/Erase 100 15 100 Max 150 50 100 15 Min 120 Max 150 50 ns s ns s Unit
Figure 14. Read and Write AC Waveforms, RP Related
READ
PROGRAM / ERASE
W
ADQ7
VALID
ADQ7
VALID
RP tPLPH tPHQ7V1,2 tPLQ7V
AI90122
39/49
M59MR032C, M59MR032D
Table 34. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70C; VDD = V DDQ = 1.65V to 2.0V, VPP = VDD unless otherwise specified)
Parameter Parameter Block (4 KWord) Erase (Preprogrammed) Main Block (32 KWord) Erase (Preprogrammed) Bank Erase (Preprogrammed, Bank A) Bank Erase (Preprogrammed, Bank B) Chip Program (2) Chip Program (DPG, VPP = 12V) (2) Word Program (3) Double Word Program Program/Erase Cycles (per Block) 100,000 200 200 Min Max (1) 2.5 10 Typ 0.15 1 2 10 20 10 10 10 10 10 Typical after 100k W/E Cycles 0.4 3 6 30 25 Unit sec sec sec sec sec sec s s cycles
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or erase should perform significantly better. 2. Excludes the time needed to execute the sequence for program instruction. 3. Same timing value if VPP = 12V.
Table 35. Data Polling and Toggle Bits AC Characteristics (1) (TA = -40 to 85 C; VDD = V DDQ = 1.65V to 2.0V)
Symbol tEHQ7V Chip Enable High to DQ7 Valid (Block Erase, E Controlled) Chip Enable High to Output Valid (Program) tEHQV tQ7VQV tWHQ7V Chip Enable High to Output Valid (Block Erase) Q7 Valid to Output Valid (Data Polling) Write Enable High to DQ7 Valid (Program, W Controlled) Write Enable High to DQ7 Valid (Block Erase, W Controlled) Write Enable High to Output Valid (Program) Write Enable High to Output Valid (Block Erase) 10 1.0 10 1.0 1.0 10 1.0 10 200 10 0 200 10 200 10 sec s sec ns s sec s sec Parameter Chip Enable High to DQ7 Valid (Program, E Controlled) Min 10 Max 200 Unit s
tWHQV
Note: 1. All other timings are defined in Read AC Characteristics table.
40/49
tEHQ7V tELQV
E
G tGLQV
W tWHQ7V DQ7 VALID
ADQ7
ADQ0-ADQ6/ ADQ8-ADQ15
IGNORE tQ7VQV
VALID
DATA PHASE OF LAST WRITE CYCLE OF PROGRAM OR ERASE INSTRUCTION
DATA POLLING READ CYCLE
Figure 15. Data Polling ADQ7 AC Waveforms (when Configuration Register bit CR15 = 1)
AI90123
M59MR032C, M59MR032D
Note: Latch Enable (L) = High.
41/49
42/49
tWHQV TOGGLE tGLQV TOGGLE STOP TOGGLE VALID DATA TOGGLE READ CYCLE
AI90124
M59MR032C, M59MR032D
E
G
W
ADQ6,ADQ2
Figure 16. Data Toggle DQ6, DQ2 AC Waveforms (when Configuration Register bit CR15 = 1)
DATA PHASE OF LAST WRITE CYCLE OF PROGRAM OF ERASE INSTRUCTION
M59MR032C, M59MR032D
Figure 17. Data Polling Flowchart Figure 18. Data Toggle Flowchart
START
START
READ DQ5 & DQ7 at VALID ADDRESS
READ DQ5 & DQ6
DQ7 = DATA NO NO
YES
DQ6 = TOGGLES YES NO
NO
DQ5 =1 YES READ DQ7
DQ5 =1 YES READ DQ6
DQ7 = DATA NO FAIL
YES
DQ6 = TOGGLES YES PASS FAIL
NO
PASS
AI90125 AI90126
43/49
M59MR032C, M59MR032D
Table 36. Ordering Information Scheme
Example: Device Type M59 Architecture M = Multiplexed Address/Data, Dual Bank, Burst Mode Operating Voltage R = 1.8V Device Function 032C = 32 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot 032D = 32 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot Speed 100 = 100 ns 120 = 120 ns Package ZC = LFBGA54: 0.5 mm pitch GC = BGA46: 0.5 mm pitch Temperature Range 6 = -40 to 85C Option T = Tape & Reel packing M59MR032C 100 GC 6 T
Devices are shipped from the factory with the memory content bits erased to '1'.
Table 37. Daisy Chain Ordering Scheme
Example: Device Type M59MR032 Daisy Chain -GC = BGA46: 0.5 mm pitch Option T = Tape & Reel Packing M59MR032 -GC T
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
44/49
M59MR032C, M59MR032D
Table 38. Revision History
Date July 1999 Version -01 First Issue FBGA Connections change FBGA Package Mechanical Data and Outline change FBGA Daisy Chain diagrams added BGA Package added Document type: from Product Preview to Preliminary Data Bus Invert (BINV) configuration bit clarification Read Operations clarification Status Register clarification LFBGA Package Mechanical Data change BGA Package Mechanical Data change BGA Package Mechanical Data change CFI Primary Algorithm modified CFI Burst Read modified Write AC Waveforms diagrams change (Figure 12, 13) Document type: from Preliminary Data to Data Sheet LFBGA Connection change (Figure 2) BGA Connection change (Figure 3) Program Time clarification (Table 33) LFBGA Package Mechanical Data and Outline change (Table 39, Figure 19) BGA Package Mechanical Data and Outline change (Table 40, Figure 20) BGA Package Mechanical Data and Outline change (Table 40, Figure 20) BGA Package Mechanical Data change (Table 40) Revision Details
12/01/99
-02
3/23/00
-03
5/17/00 9/26/00
-04 -05
12/20/00
-06
3/02/01 3/19/01
-07 -08
45/49
M59MR032C, M59MR032D
Table 39. LFBGA54 - 10 x 4 ball array, 0.5 mm pitch, Package Mechanical Data
millimeters Symbol A A1 A2 b D D1 ddd e E E1 E2 E3 E4 FD FE SD SE 0.500 12.000 1.500 6.500 1.000 0.500 1.250 5.250 0.250 0.250 - 11.800 - - - - - - - - Typ 1.100 0.150 0.950 0.400 7.000 4.500 Min 1.000 0.100 - 0.300 6.800 - Max 1.200 0.250 - 0.450 7.200 - 0.150 - 12.200 - - - - - - - - 0.0197 0.4724 0.0591 0.2559 0.0394 0.0197 0.0492 0.2067 0.0098 0.0098 - 0.4646 - - - - - - - - Typ 0.0433 0.0059 0.0374 0.0157 0.2756 0.1772 inches Min 0.0394 0.0039 - 0.0118 0.2677 - Max 0.0472 0.0098 - 0.0177 0.2835 - 0.0059 - 0.4803 - - - - - - - -
Figure 19. LFBGA54 - 10 x 4 ball array, 0.5 mm pitch, Bottom View Package Outline
D D1 SD FD
E4 E3 FE
E
E2
E1
SE
ddd
DUMMY BALLS BALL "A1"
A
e
b A1
A2
BGA-Z06
Drawing is not to scale. 46/49
M59MR032C, M59MR032D
Table 40. BGA46 - 10 x 4 ball array, 0.5 mm pitch, Package Mechanical Data
Symbol A A1 A2 b D D1 D2 D3 ddd e E E1 E2 E3 FD FD1 FD2 FE FE1 FE2 SD SE Typ millimeters Min 0.150 0.700 0.320 10.530 4.500 6.500 8.500 0.500 6.290 1.500 3.500 5.500 3.015 2.015 1.015 2.395 1.395 0.395 0.250 0.250 0.250 10.480 - - - - 6.240 - - - - - - - - - - - 0.400 10.580 - - - 0.080 - 6.340 - - - - - - - - - - - 0.0276 0.0126 0.4146 0.1772 0.2559 0.3346 0.0197 0.2476 0.0591 0.1378 0.2165 0.1187 0.0793 0.0400 0.0943 0.0549 0.0156 0.0098 0.0098 Max 1.000 Typ inches Min 0.0059 0.0098 0.4126 - - - - 0.2457 - - - - - - - - - - - 0.0157 0.4165 - - - 0.0031 - 0.2496 - - - - - - - - - - - Max 0.0394
Figure 20. BGA46 - 10 x 4 ball array, 0.5 mm pitch, Bottom View Package Outline
D D3 D2 D1 FE FE1 FE2 SD
E1 e SE
E2
E3
E
BALL "A1"
FD2 FD1 FD
b DUMMY BALLS
ddd
A
A1
A2
BGA-G07
Drawing is not to scale. 47/49
M59MR032C, M59MR032D
Figure 21. BGA46 Daisy Chain - Package Connections (Top view through package)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
AI90127
Figure 22. BGA46 Daisy Chain - PCB Connections proposal (Top view through package)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B START POINT C
D
E
F
G END POINT H
AI90128
48/49
M59MR032C, M59MR032D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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